科研论文
New
2026
Tackling MoE communication bottleneck with dynamic in-switch computing on multi-GPUs
. Ji, J. Leng, G. He, and M. Guo, “Tackling MoE communication bottleneck with dynamic in-switch computing on multi-GPUs,” in Proceedings of the 53rd Annual International Symposium on Computer Architecture (ISCA), Raleigh, USA, 2026....
New
2026
MoE-Hub: Taming Software Complexity for Seamless MoE Overlap with Hardware-Accelerated Communication on Multi-GPU Systems
Z. Ji, J. Leng, G. He, and M. Guo, “MoE-Hub: Taming software complexity for seamless MoE overlap with hardware-accelerated communication on multi-GPU systems,” in Proceedings of the 53rd Annual International Symposium on Computer Architecture (ISCA), Raleigh, USA, 2026....
Top
2020
Exploring the Impact of Random Telegraph Noise-Induced Accuracy Loss on Resistive RAM-Based Deep Neural Network
oring the Impact of Random Telegraph Noise-Induced Accuracy Loss on Resistive RAM-Based Deep Neural Network,” IEEE Trans. Electron Devices, vol. 67, no. 8, pp. 3335-3340, Jun. 2020....
2026
Tackling MoE communication bottleneck with dynamic in-switch computing on multi-GPUs
Q. Zhang, C. Zhang, Z. Zhou, H. Wang, Z. Zhou, Z. Tu, G. Sun, Z. Xie, Y. Diao, Z. Ji, J. Leng, G. He, and M. Guo, “Tackling MoE communication bottleneck with dynamic in-switch computing on multi-GPUs,” in Proceedings of the 53rd Annual International Symposium on Computer Architecture (ISCA), Raleigh, USA, 2026.
PDF
2026
MoE-Hub: Taming Software Complexity for Seamless MoE Overlap with Hardware-Accelerated Communication on Multi-GPU Systems
Z. Zhou, C. Zhang, S. Zhang, Q. Zhang, H. Wang, Z. Zhou, Z. Tu, G. Sun, Y. Diao, Z. Ji, J. Leng, G. He, and M. Guo, “MoE-Hub: Taming software complexity for seamless MoE overlap with hardware-accelerated communication on multi-GPU systems,” in Proceedings of the 53rd Annual International Symposium on Computer Architecture (ISCA), Raleigh, USA, 2026.
PDF
2026
FACT: A new framework for aging-aware circuits critical path prediction with enhanced adaptability
M. Jin, Y. Wei, Y. Sun, F. Shu, H. Chen, P. Ren, R. Wang, and Z. Ji, “FACT: A new framework for aging-aware circuits critical path prediction with enhanced adaptability,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., 2026.
PDF
2026
Recent advances in contact resistivity at metal-semiconductor interfaces for post-Moore nanoscale devices
M. Wu, M. Yuan, H. Lin, H. Dong, F. Lu, W. Wang, S. Ye, and Z. Ji, “Recent advances in contact resistivity at metal-semiconductor interfaces for post-Moore nanoscale devices,” APL Electron. Devices, vol. 2, no. 1, pp. 011501, Feb. 2026.
PDF
The reduced contact resistivity through interface doping in CoSi₂/Si system: A first-principles study
M. Yuan, M. Wu, H. Lin, F. Lu, W. Wang, S. Ye, and Z. Ji, “The reduced contact resistivity through interface doping in CoSi₂/Si system: A first-principles study,” in 2026 IEEE Electron Devices Technology & Manufacturing Conf. (EDTM), Penang, Malaysia, 2026.
PDF
2026
Comprehensive study on interfacial layer and oxygen vacancy suppression via scavenging electrodes in ferroelectric MFS capacitors
B. Cui, J. Liu, C. Zhang, M. Wu, S. Ye, X. Wang, Y. Wu, M. Yuan, Y. Wen, H. Lu, D. Zhang, R. Wang, and Z. Ji, “Comprehensive study on interfacial layer and oxygen vacancy suppression via scavenging electrodes in ferroelectric MFS capacitors,” in Proc. 2026 IEEE Electron Devices Technology & Manufacturing Conf. (EDTM), Penang, Malaysia, 2026.
PDF
2026
Theoretical insights into interfacial-layer control of Fermi level depinning and dipole engineering for Schottky barrier height reduction in NiSi/Si systems
M. Yuan, M. Wu, H. Lin, F. Lu, W. Wang, Z. Liu, S. Ye, R. Wang, Z. Ji, "Theoretical insights into interfacial-layer control of Fermi level depinning and dipole engineering for Schottky barrier height reduction in NiSi/Si systems," J. Vac. Sci. Technol. A, vol. 44, no.1, pp. 013202, Jan. 2026.
PDF
2026
On the understanding of aging-induced band tail states under cryogenic temperatures
C. Zhang, Y. Hu, G. Xu, M. Wu, Y. Liu, P. Ren, R. Wang, and Z. Ji, “On the understanding of aging-induced band tail states under cryogenic temperatures,” in 2026 IEEE Electron Devices Technology & Manufacturing Conf. (EDTM), Penang, Malaysia, 2026.
PDF
2026
Fast Full-chip Thermal Assessment Methodology for Emerging BSPDN Architectures
S. Wang, M. Jin, X. Zhang, Y. Zhang, Y. Xia, H. Bao, P. Ren*, and Z. Ji, "Fast Full-chip Thermal Assessment Methodology for Emerging BSPDN Architectures," in 2026 IEEE International Reliability Physics Symposium (IRPS), Tucson, AZ, USA, 2026.
PDF
2026
New Insight into the Process Variations of Advanced Nanosheet Technology: A N/PMOS Correlation Perspective
Y. Zhang, S. Wang, C. Zhang, Y. Liu, P. Ren*, and Z. Ji, "New Insight into the Process Variations of Advanced Nanosheet Technology: A N/PMOS Correlation Perspective," in 2026 IEEE International Reliability Physics Symposium (IRPS), Tucson, AZ, USA, 2026.
PDF