科研论文
New
2026
TRACE: A Transferable Framework for Aging-aware Cell delay Estimation
ork for Aging-aware Cell delay Estimation," in 2026 29th Design, Automation and Test in Europe Conference (DATE), Verona, Italy, 2026....
New
2025
Towards Design-Technology Co-optimization for Nanosheet Transistors with Backside Contact
gy Co-optimization for Nanosheet Transistors with Backside Contact," IEEE Transactions on Nanotechnology, vol. 24, pp. 439-444, Aug. 2025....
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2020
Exploring the Impact of Random Telegraph Noise-Induced Accuracy Loss on Resistive RAM-Based Deep Neural Network
oring the Impact of Random Telegraph Noise-Induced Accuracy Loss on Resistive RAM-Based Deep Neural Network,” IEEE Trans. Electron Devices, vol. 67, no. 8, pp. 3335-3340, Jun. 2020....
2026
TRACE: A Transferable Framework for Aging-aware Cell delay Estimation
M. Jin, Y. Chao, Y. Liu, Z. Cai, P. Ren and Z. Ji, "TRACE: A Transferable Framework for Aging-aware Cell delay Estimation," in 2026 29th Design, Automation and Test in Europe Conference (DATE), Verona, Italy, 2026.
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2025
Towards Design-Technology Co-optimization for Nanosheet Transistors with Backside Contact
S. Wang, P. Ren, Y. Zhang, M. Yang, R. Wang, and Z. Ji, "Towards Design-Technology Co-optimization for Nanosheet Transistors with Backside Contact," IEEE Transactions on Nanotechnology, vol. 24, pp. 439-444, Aug. 2025.
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2025
Fine-Grained Structured Sparse Computing for FPGA-Based AI Inference
C. Zhang, S. Cao, G. Dai, C. Geng, Z. Yao, W. Xiao, Y. Liu, M. Wu, L. Zhang, G. Sun, Z. Ji, R. Wang, and R. Huang, "Fine-Grained Structured Sparse Computing for FPGA-Based AI Inference," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 44, no. 7, pp. 2544-2557, Jul. 2025.
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2025
Dealing with Coupling Effect for Accurate Thermal Profile Prediction of BEOL Interconnect in Advanced Technology Nodes
S. Wang, Y. Sheng, Y. Xia, H. Bao, P. Ren, R. Wang, and Z. Ji, “Dealing with Coupling Effect for Accurate Thermal Profile Prediction of BEOL Interconnect in Advanced Technology Nodes,” APL Electronic Devices, vol.1, no.3, pp. 036108, Sep. 2025.
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2025
Charge redistribution to reduce contact resistivity in NiSi/Si system through interface modification: A first-principles study
M. Yuan, M. Wu, Y. Wen, Y. Hu, X. Wang, B. Cui, J. Liu, Y. Wu, H. Dong, F. Lu, W. Wang, P. Ren, S. Ye, H. Lu, R. Wang, and Z. Ji, "Charge redistribution to reduce contact resistivity in NiSi/Si system through interface modification: A first-principles study," Appl. Phys. Lett. vol. 126, pp. 131601, Mar. 2025.
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2025
DATIS: DRAM Architecture and Technology Integrated Simulation
S. Xia, C. Zhang, G. Sun, G Dai, R. Wang, Z. Ji, and R. Huang, ”DATIS: DRAM Architecture and Technology Integrated Simulation,” in 2025 3rd International Symposium of Electronics Design Automation (ISEDA), Hong Kong, China, 2025, pp. 534-541.
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2025
Towards Accurate Machine-learning-assisted Aging Prediction with Probabilistic Strategy
X. Qiu, D. An, Y. Wang, P. Ren, and Z. Ji, ”Towards Accurate Machine-learning-assisted Aging Prediction with Probabilistic Strategy,” in 2025 3rd International Symposium of Electronics Design Automation (ISEDA), Hong Kong, China, 2025, pp. 669-673.
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2025
New Approach for Aging Assessment of Digital Circuits Featuring Systematic Signal Probability Tracing
Y. Sun, F. Shu, M. Jin, P. Ren, R. Wang, and Z. Ji, "New Approach for Aging Assessment of Digital Circuits Featuring Systematic Signal Probability Tracing," in 2025 3rd International Symposium of Electronics Design Automation (ISEDA), Hong Kong, China, 2025, pp. 513-520.
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2025
Charge balance effect on the phase stability and reliability in doped HfO2-ZrO2 superlattice films for further DRAM capacitors: A first-principles study
T. Zhang, M. Wu, M. Yuan, Y. Wen, Y. Hu, X. Wang, B. Cui, J. Liu, Y. Wu, H. Dong, F. Lu, W. Wang, P. Ren, S. Ye, H. Lu, R. Wang, Z. Ji, and R. Huang, "Charge balance effect on the phase stability and reliability in doped HfO2-ZrO2 superlattice films for further DRAM capacitors: A first-principles study," Appl. Phys. Lett., vol. 126, no. 10, pp. 102901, Mar. 2025.
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2025
Bit Line Hammering in Si-Based VCT DRAM: A New Security Challenge and Its Mitigation
Y. Liu, D. Wang, P. Ren, R. Wang, Z. Ji, and R. Huang, "Bit Line Hammering in Si-Based VCT DRAM: A New Security Challenge and Its Mitigation," IEEE Electron Device Letters, vol. 46, no. 5, pp. 733-736, Mar. 2025.
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