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The reduced contact resistivity through interface doping in CoSi₂/Si system: A first-principles study
resistivity through interface doping in CoSi₂/Si system: A first-principles study,” in 2026 IEEE Electron Devices Technology & Manufacturing Conf. (EDTM), Penang, Malaysia, 2026....
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2026
Recent advances in contact resistivity at metal-semiconductor interfaces for post-Moore nanoscale devices
ances in contact resistivity at metal-semiconductor interfaces for post-Moore nanoscale devices,” APL Electron. Devices, 2026....
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2020
Exploring the Impact of Random Telegraph Noise-Induced Accuracy Loss on Resistive RAM-Based Deep Neural Network
oring the Impact of Random Telegraph Noise-Induced Accuracy Loss on Resistive RAM-Based Deep Neural Network,” IEEE Trans. Electron Devices, vol. 67, no. 8, pp. 3335-3340, Jun. 2020....
The reduced contact resistivity through interface doping in CoSi₂/Si system: A first-principles study
M. Yuan, M. Wu, H. Lin, F. Lu, W. Wang, S. Ye, and Z. Ji, “The reduced contact resistivity through interface doping in CoSi₂/Si system: A first-principles study,” in 2026 IEEE Electron Devices Technology & Manufacturing Conf. (EDTM), Penang, Malaysia, 2026.
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2026
Recent advances in contact resistivity at metal-semiconductor interfaces for post-Moore nanoscale devices
M. Wu, M. Yuan, H. Lin, H. Dong, F. Lu, W. Wang, S. Ye, and Z. Ji, “Recent advances in contact resistivity at metal-semiconductor interfaces for post-Moore nanoscale devices,” APL Electron. Devices, 2026.
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2026
Theoretical insights into interfacial-layer control of Fermi level depinning and dipole engineering for Schottky barrier height reduction in NiSi/Si systems
M. Yuan, M. Wu, H. Lin, F. Lu, W. Wang, Z. Liu, S. Ye, R. Wang, Z. Ji, "Theoretical insights into interfacial-layer control of Fermi level depinning and dipole engineering for Schottky barrier height reduction in NiSi/Si systems," J. Vac. Sci. Technol. A, vol. 44, no.1, pp. 013202, Jan. 2026.
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2026
On the understanding of aging-induced band tail states under cryogenic temperatures
C. Zhang, Y. Hu, G. Xu, M. Wu, Y. Liu, P. Ren, R. Wang, and Z. Ji, “On the understanding of aging-induced band tail states under cryogenic temperatures,” in 2026 IEEE Electron Devices Technology & Manufacturing Conf. (EDTM), Penang, Malaysia, 2026.
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2026
Fast Full-chip Thermal Assessment Methodology for Emerging BSPDN Architectures
S. Wang, M. Jin, X. Zhang, Y. Zhang, Y. Xia, H. Bao, P. Ren*, and Z. Ji, "Fast Full-chip Thermal Assessment Methodology for Emerging BSPDN Architectures," in 2026 IEEE International Reliability Physics Symposium (IRPS), Tucson, AZ, USA, 2026.
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2026
New Insight into the Process Variations of Advanced Nanosheet Technology: A N/PMOS Correlation Perspective
Y. Zhang, S. Wang, C. Zhang, Y. Liu, P. Ren*, and Z. Ji, "New Insight into the Process Variations of Advanced Nanosheet Technology: A N/PMOS Correlation Perspective," in 2026 IEEE International Reliability Physics Symposium (IRPS), Tucson, AZ, USA, 2026.
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2025
Design rule for morphotropic phase boundary formation in Hf-based material system with high permittivity, low leakage and low thermal budget
M. Wu, S. Ye, X. Wang, J. Liu, Y. Hu, H. Lin, B. Cui, Y. Wen, Y. Wu, T. Zhang, H. Dong, F. Lu, W. Wang, P. Ren, H. Lu, Z. Liu, R. Wang, and Z. Ji*, "Design rule for morphotropic phase boundary formation in Hf-based material system with high permittivity, low leakage and low thermal budget," npj Comput. Mater., Dec. 2025.
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2025
Hafnium oxide-based nonvolatile ferroelectric memcapacitor array for high energy-efficiency neuromorphic computing
X. Wang, S. Ye, B. Cui, Y. Li, Y. Wei, Y. Xiao, J. Liu, Z. Huang, Y. Wu, Y. Wen, Z. Wang, M. Wu, P. Ren, H. Fang, H. Lu, R. Wang, Z. Ji, and R. Huang, “Hafnium oxide-based nonvolatile ferroelectric memcapacitor array for high energy-efficiency neuromorphic computing,” Nano Energy, vol. 140, pp. 111011, Jul. 2025.
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2026
TRACE: A Transferable Framework for Aging-aware Cell delay Estimation
M. Jin, Y. Chao, Y. Liu, Z. Cai, P. Ren and Z. Ji, "TRACE: A Transferable Framework for Aging-aware Cell delay Estimation," in 2026 29th Design, Automation and Test in Europe Conference (DATE), Verona, Italy, 2026.
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2025
Towards Design-Technology Co-optimization for Nanosheet Transistors with Backside Contact
S. Wang, P. Ren, Y. Zhang, M. Yang, R. Wang, and Z. Ji, "Towards Design-Technology Co-optimization for Nanosheet Transistors with Backside Contact," IEEE Transactions on Nanotechnology, vol. 24, pp. 439-444, Aug. 2025.
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