2022年9月28日，本课题组王达同学在微电子领域权威期刊IEEE Transactions on Electron Devices发表题为“Defect-based Empirical Model for On-State Degradation in sub-20nm DRAM Periphery pFETs under Arbitrary Condition”文章，纪志罡教授、任鹏鹏副教授和王润声教授为共同通讯作者。

这篇文章提出了一种适用于亚20nm DRAM 节点的外围晶体管的老化模型，可以准确预测器件在开态条件下任意应力条件下的退化情况。该工作将底层缺陷和器件长期可靠性紧密联系，有助于未来DRAM外围电路中工艺优化和器件/电路协同优化的发展。

Abstract：

This work investigates the on-state degradation under arbitrary stress conditions for periphery pFETs fabricated in the sub-20nm DRAM technology. Three types of traps are identified, including the interface states, the oxide hole traps and the oxide electron traps. By analyzing the time dependence, stress dependence, and lateral position, the generation mechanism for each type of trap is revealed, based on which a defect-based model was established. We proposed an effective model parameter extraction strategy and thus avoided overfitting. The predictive capability of the proposed model is further verified across the full bias regions at lower voltage conditions, including operating conditions. Finally, based on the model, the contributions of different types of traps to the degradation can be derived throughout the device’s entire lifetime. The work paves ways to link the defects to the device’s long-term reliability, which can be helpful for future process optimization and device/circuit co-optimization in DRAM peripheral circuits.